SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
A high-performance microarchitecture with hardware-programmable functional units
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Programmable active memories: reconfigurable systems come of age
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wormhole run-time reconfiguration
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Improving functional density through run-time constant propagation
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Configuration prefetch for single context reconfigurable coprocessors
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Signal processing at 250 MHz using high-performance FPGA's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A reconfigurable arithmetic array for multimedia applications
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
PipeRench: a co/processor for streaming multimedia acceleration
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing
IEEE Transactions on Computers
Reconfigurable computing: what, why, and implications for design automation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A HW/SW partitioning algorithm for dynamically reconfigurable architectures
Proceedings of the conference on Design, automation and test in Europe
A bitstream reconfigurable FPGA implementation of the WSAT algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Re-configurable computing in wireless
Proceedings of the 38th annual Design Automation Conference
A dynamically reconfigurable adaptive viterbi decoder
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Reconfigurable Computing for Digital Signal Processing: A Survey
Journal of VLSI Signal Processing Systems
The Garp Architecture and C Compiler
Computer
AnyBoard: An FPGA-Based, Reconfigurable System
IEEE Design & Test
Evolution of Digital Filters Using a Gate Array Model
EvoIASP '99/EuroEcTel '99 Proceedings of the First European Workshops on Evolutionary Image Analysis, Signal Processing and Telecommunications
A New Research Tool for Intrinsic Hardware Evolution
ICES '98 Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware
Intrinsic Circuit Evolution Using Programmable Analogue Arrays
ICES '98 Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware
Hardware-software bipartitioning for dynamically reconfigurable systems
Proceedings of the tenth international symposium on Hardware/software codesign
Architecture Design of Reconfigurable Pipelined Datapaths
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
The MorphoSys Dynamically Reconfigurable System-on-Chip
EH '99 Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware
Artificial Evolution of Active Filters: A Case Study
EH '99 Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware
On the Filtering Properties of Evolved Gate Arrays
EH '99 Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware
Prototyping a GA Pipeline for Complete Hardware Evolution
EH '99 Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware
Evolutionary Design of Single Electron Systems
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
Evolving an Adaptive Digital Filter
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
The Chimaera reconfigurable functional unit
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Real-time stereo vision on the PARTS reconfigurable computer
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
A dynamic reconfiguration run-time system
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Compilation tools for run-time reconfigurable designs
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Incremental reconfiguration for pipelined applications
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Computing kernels implemented with a wormhole RTR CCM
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
A Run-Time Reconfigurable Engine for Image Interpolation
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
JHDL - An HDL for Reconfigurable Systems
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Dynamic Specialization of XC6200 FPGAs by Partial Evaluation
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
An Effective Design System for Dynamically Reconfigurable Architectures
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
The Design and Implementation of a Context Switching FPGA
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Analysis of the XC6000 Architecture for Embedded System Design
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Automating Production of Run-Time Reconfigurable Designs
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
The NAPA Adaptive Processing Architecture
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
ICARUS: A Dynamically Reconfigurable Computer Architecture
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Runlength Compression Techniques for FPGA Configurations
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A Virtual Hardware Handler for RTR Systems
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A CAD Suite for High-Performance FPGA Design
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A Virtual Hardware System on a Dynamically Reconfigurable Logic Device
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Configuration Relocation and Defragmentation for Reconfigurable Computing
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Reconfigurable Array Media Processor (RAMP)
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Configuration Caching Management Techniques for Reconfigurable Computing
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Adapting Constant Multipliers in a Neural Network Implementation
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Combining Serialization and Reconfiguration for Convolver Designs
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
MorphoSys: A Reconfigurable Architecture for Multimedia Applications
SBCCI '98 Proceedings of the 11th Brazilian Symposium on Integrated circuit design
Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Bridging The Genotype-Phenotype Mapping For Digital Fpgas
EH '01 Proceedings of the The 3rd NASA/DoD Workshop on Evolvable Hardware
Progress And Challenges In Building Evolvable Devices
EH '01 Proceedings of the The 3rd NASA/DoD Workshop on Evolvable Hardware
Pama - Programmable Analog Multiplexer Array
EH '01 Proceedings of the The 3rd NASA/DoD Workshop on Evolvable Hardware
Design methodologies for partially reconfigured systems
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Issues in wireless video coding using run-time-reconfigurable FPGAs
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
A dynamic instruction set computer
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Run-Time Execution of Reconfigurable Hardware in a Java Environment
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
ACE card(tm): A High Performance Architecture for Run-Time Reconfiguration
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
Design and Implementation of a Coarse-Grained Dynamically Reconfigurable Hardware Architecture
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
Explorations in design space: unconventional electronics designthrough artificial evolution
IEEE Transactions on Evolutionary Computation
Configuration compression for the Xilinx XC6200 FPGA
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Video communications using rapidly reconfigurable hardware
IEEE Transactions on Circuits and Systems for Video Technology
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Today's digital signal processing (DSP) applications use computationally complex and/or adaptive algorithms and have stringent requirements in terms of speed, size, cost, power consumption, and throughput. Efficient hardware implementation techniques should be employed to meet the requirements of these applications. Run-Time Reconfiguration (RTR) is a promising technique for reducing the hardware required for implementing DSP systems as well as improving the performance, speed and power consumption of these systems. In this survey, we explain different issues in run-time reconfigurable systems and list the implemented systems which support run-time reconfiguration. We also describe different applications of run-time reconfiguration and discuss the improvements achieved by applying run-time reconfiguration.