DATE '00 Proceedings of the conference on Design, automation and test in Europe
Configuration compression for FPGA-based embedded systems
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Hybrid Data/Configuration Caching for Striped FPGAs
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
An Adaptive Cryptographic Engine for IPSec Architectures
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Modeling and optimizing run-time reconfiguration using evolutionary computation
ACM Transactions on Embedded Computing Systems (TECS)
Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey
Journal of VLSI Signal Processing Systems
Optically Differential Reconfigurable Gate Array Using an Optical System with VCSELs
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Hyperreconfigurable architectures and the partition into hypercontexts problem
Journal of Parallel and Distributed Computing
Configuration bitstream compression for dynamically reconfigurable FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Run-time reconfigurable systems for digital signal processing applications: a survey
Journal of VLSI Signal Processing Systems
A new decompression system for the configuration process of SRAM-based FPGAS
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Design Aspects of Multi-level Reconfigurable Architectures
Journal of Signal Processing Systems
Multi-level reconfigurable architectures in the switch model
Journal of Systems Architecture: the EUROMICRO Journal
Configuration compression for FPGA-based embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Decoding-aware compression of FPGA bitstreams
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A configuration system architecture supporting bit-stream compression for FPGAs
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
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One of the major overheads in reconfigurable computing is the time it takes to reconfigure the devices in the system. This overhead limits the speedups possible in this exciting new paradigm. In this paper me explore one technique for reducing this overhead: the compression of configuration datastreams. We develop an algorithm, targeted to the decompression hardware imbedded in the Xilinx XC6200 series field-programmable gate array architecture, that can radically reduce the amount of data needed to transfer during reconfiguration. This results in an overall reduction of about a factor of four in total bandwidth required for reconfiguration