Dynamic reconfiguration of FPGAs
Selected papers from the Oxford 1993 international workshop on field programmable logic and applications on More FPGAs
Genetic algorithms + data structures = evolution programs (3rd ed.)
Genetic algorithms + data structures = evolution programs (3rd ed.)
Scheduling designs into a time-multiplexed FPGA
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Codesign of embedded systems based on Java and reconfigurable hardware components
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Hardware-software co-design of embedded reconfigurable architectures
Proceedings of the 37th Annual Design Automation Conference
Partitioning and pipelining for performance-constrained hardware/software systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A HW/SW partitioning algorithm for dynamically reconfigurable architectures
Proceedings of the conference on Design, automation and test in Europe
Hardware resource allocation for hardware/software partitioning in the LYCOS system
Proceedings of the conference on Design, automation and test in Europe
Hardware/software partitioning with integrated hardware design space exploration
Proceedings of the conference on Design, automation and test in Europe
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Discrete Time Processing of Speech Signals
Discrete Time Processing of Speech Signals
Development of a Run-Time Reconfiguration System with Low Reconfiguration Overhead
Journal of VLSI Signal Processing Systems
Scheduling for Embedded Real-Time Systems
IEEE Design & Test
Automatc identification of swappable logic units in XC6200 circuitry
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
A hardware/software partitioning algorithm for custom computing machines
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Hardware-Software Codesign for Dynamically Reconfigurable Architectures
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
Implementation Approaches for Reconfigurable Logic Applications
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
Two-Level Hardware/Software Partitioning Using CoDe-X
ECBS '96 Proceedings of the IEEE Symposium and Workshop on Engineering of Computer Based Systems
PACE: A Dynamic Programming Algorithm for Hardware/Software Partitioning
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
Compilation tools for run-time reconfigurable designs
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Fast Partial Reconfiguration for FCCMs
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Accelerating Run-Time Reconfiguration on FCCMs
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Reconfigurable architectures for general-purpose computing
Reconfigurable architectures for general-purpose computing
Improving functional density through run-time circuit reconfiguration
Improving functional density through run-time circuit reconfiguration
Configuration compression for the Xilinx XC6200 FPGA
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
The minimization of hardware size in reconfigurable embedded platforms
Proceedings of the 2008 ACM symposium on Applied computing
A Flexible system level design methodology targeting run-time reconfigurable FPGAs
EURASIP Journal on Embedded Systems - Reconfigurable Computing and Hardware/Software Codesign
Run-time reconfigurable RTOS for reconfigurable systems-on-chip
Journal of Embedded Computing - Selected papers of EUC 2005
Customized kernel execution on reconfigurable hardware for embedded applications
Microprocessors & Microsystems
Task Scheduling for Context Minimization in Dynamically Reconfigurable Platforms
Journal of Signal Processing Systems
Task scheduling for context minimization in dynamically reconfigurable platforms
EUC'07 Proceedings of the 2007 international conference on Embedded and ubiquitous computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A run-time partitioning algorithm for RTOS on reconfigurable hardware
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
| Hi-index | 0.00 |
The hardware--software (HW--SW) partitioning of applications to dynamically reconfigurable embedded systems allows for customization of their hardware resources during run-time to meet the demands of executing applications. The run-time reconfiguration (RTR) of such systems can have an impact on the HW--SW partitioning strategy and the system performance. It is therefore important to consider approaches to optimally reduce the RTR overhead during the HW--SW partitioning stage. In order to examine potential benefits in performance, it is necessary to develop a method to model and evaluate the RTR. In this paper, a novel method of modeling and evaluating such RTR-reduced HW--SW partitions is presented. The techniques of computation-reconfiguration overlap and the retention of circuitry between reconfigurations are used within this model to explore the possibilities of RTR reduction. The integration of this model into the authors' current genetic-algorithm-driven HW--SW partitioner is also presented, with two applications used to illustrate the benefits of RTR-reduced exploration during HW--SW partitioning.