System Synthesis with VHDL: A Transformational Approach
System Synthesis with VHDL: A Transformational Approach
Designing an Operating System for a Heterogeneous Reconfigurable SoC
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Hardware support for real-time operating systems
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Hard Real-time Computing Systems: Predictable Scheduling Algorithms And Applications (Real-Time Systems Series)
Modeling and optimizing run-time reconfiguration using evolutionary computation
ACM Transactions on Embedded Computing Systems (TECS)
Rate monotonic vs. EDF: judgment day
Real-Time Systems
The Development of an Operating System for Reconfigurable Computing
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A comparison of the RTU hardware RTOS with a hardware/software RTOS
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A run-time partitioning algorithm for RTOS on reconfigurable hardware
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
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High computational performance and flexibility are the requirements of nowadays embedded systems and they are increasing constantly. Moreover, a single architecture must be able to support different applications with dynamically requirements (changing environments). Reconfigurable computing based on hybrid architectures, comprising general purpose processor (CPU) and Field Programmable Gate Array (FPGA), is very attractive because it can provide high computational performance as well as flexibility to support the requirements of today's embedded systems. As an Operating System (OS) is desired to provide support for such systems, it has to use the available resources in an optimal way (competing with the application), since an embedded system architecture usually lack of resources. Therefore, we present here our approach towards a reconfigurable RTOS that is able to distribute itself over a hybrid architecture (comprising FPGA and CPU). In this work we will present the main concepts and methods used to achieve the desired RTOS. Moreover, we present some preliminary evaluation results which show the applicability of our approach.