A dynamic memory management unit for embedded real-time system-on-a-chip
CASES '00 Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems
A novel parallel deadlock detection algorithm and architecture
Proceedings of the ninth international symposium on Hardware/software codesign
Proceedings of the 38th annual Design Automation Conference
A system-on-a-chip lock cache with task preemption support
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Co-Synthesis of Hardware and Software for Digital Embedded Systems
Co-Synthesis of Hardware and Software for Digital Embedded Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A hardware/software kernel for system on chip designs
Proceedings of the 2004 ACM symposium on Applied computing
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Run-time reconfigurable RTOS for reconfigurable systems-on-chip
Journal of Embedded Computing - Selected papers of EUC 2005
Journal of Systems and Software
Task management in MPSoCs: an ASIP approach
Proceedings of the 2009 International Conference on Computer-Aided Design
SCMP architecture: an asymmetric multiprocessor system-on-chip for dynamic applications
Proceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies
Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A run-time partitioning algorithm for RTOS on reconfigurable hardware
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
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In this paper, we show the performance comparison and analysis result among three RTOSes: the Real-Time Unit (RTU) hardware RTOS, the pure software Atalanta RTOS and a hardware/software RTOS composed of part of Atalanta interfaced to the System-on-a-Chip Lock Cache (SoCLC) hardware. We also present our RTOS configuration framework that can automatically configure these three RTOSes. The average-case simulation result of a database application example on a three-processor system running thirty tasks with RTU and the same system with SoCLC showed 36% and 19% overall speedups, respectively, as compared to the pure software RTOS system.