Proceedings of the conference on Design, automation and test in Europe
A Hardware-Software Real-Time Operating System Framework for SoCs
IEEE Design & Test
A System-on-Chip Implementation of the IEEE 802.11a MAC Layer
DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
Full TCP/IP for 8-bit architectures
Proceedings of the 1st international conference on Mobile systems, applications and services
An Open TCP/IP Core for Reconfigurable Logic
FCCM '05 Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A comparison of the RTU hardware RTOS with a hardware/software RTOS
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
TCP offload is a dumb idea whose time has come
HOTOS'03 Proceedings of the 9th conference on Hot Topics in Operating Systems - Volume 9
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware/Software Partitioning Using Bayesian Belief Networks
IEEE Transactions on Systems, Man, and Cybernetics, Part A: Systems and Humans
Architectural partitioning for system level synthesis of integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design of high-performance system-on-chips using communication architecture tuners
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We present an issue of the dynamically reconfigurable hardware-software architecture which allows for partitioning networking functions on a SoC (System on Chip) platform. We address this issue as a partition problem of implementing network protocol functions into dynamically reconfigurable hardware and software modules. Such a partitioning technique can improve the co-design productivity of hardware and software modules. Practically, the proposed partitioning technique, which is called the ITC (Inter-Task Communication) technique incorporating the RT-IJC^2 (Real-Time Inter-Job Communication Channel), makes it possible to resolve the issue of partitioning networking functions into hardware and software modules on the SoC platform. Additionally, the proposed partitioning technique can support the modularity and reuse of complex network protocol functions, enabling a higher level of abstraction of future network protocol specifications onto the SoC platform. Especially, the RT-IJC^2 allows for more complex data transfers between hardware and software tasks as well as provides real-time data processing simultaneously for given application-specific real-time requirements. We conduct a variety of experiments to illustrate the application and efficiency of the proposed technique after implementing it on a commercial SoC platform based on the Altera's Excalibur including the ARM922T core and up to 1 million gates of programmable logic.