Architectural partitioning for system level synthesis of integrated circuits

Authors:
E. D. Lagnese;D. E. Thomas
Affiliations:
Dept. of Eletr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA;-
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2006

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Abstract

APARTY is an architectural partitioning tool that uses a novel multistage clustering algorithm to extract the high level structure of an IC design by concentrating on area and interconnect considerations. Performance is addressed implicitly. APARTY works within the framework of the system architect's workbench and can pass system-level structural information along to register-transfer level (RTL) tools to guide the completion of a data-path design. The multistage clustering algorithm and how it is used by APARTY to choose partitions are described. The system architect's workbench and how architectural partitioning can be used to guide synthesis are also described. Results of using APARTY in the design process show improved register-transfer designs. In particular, the number of global routing wires is generally reduced by over 50% by following the partitioning scheme suggested by APARTY