Specification partitioning for system design
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Power-profiler: optimizing ASICs power consumption at the behavioral level
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Low-power architectural synthesis and the impact of exploiting locality
Journal of VLSI Signal Processing Systems - Special issue on technologies for wireless computing
Scheduling techniques for variable voltage low power designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Datapath scheduling with multiple supply voltages and level converters
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scheduling with multiple voltages
Integration, the VLSI Journal
Energy minimization using multiple supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Optimal synthesis of multichip architectures
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Synthesis of VLSI systems with the CAMAD design aid
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A low power scheduling scheme with resources operating at multiple voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Model and Methodology for Hardware-Software Codesign
IEEE Design & Test
A Hardware-Software Codesign Methodology for DSP Applications
IEEE Design & Test
Computer-aided partitioning of behavioral hardware descriptions
DAC '83 Proceedings of the 20th Design Automation Conference
Architectural partitioning for system level synthesis of integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a novel resource-constrained synthesis scheme to minimize power consumption with resources operating at multiple voltages. The inputs to our scheme are (i) unscheduled data flow graph, (ii) library containing a table of delays and supply voltages for the resources and (iii) resource constraints given as the number and the type of functional units to be used. The proposed scheme, with polynomial time complexity, runs in three phases. In the first phase, operations are scheduled to minimize the number of control steps, and in the meantime, they are assigned to resources operating at reduced voltages. In the second phase, operations are clustered to form proper voltage islands to minimize interconnection costs. In the last phase, operations are rescheduled and permanently bound to sources, which will satisfy the given resource constraints. At this point, rescheduling is necessary to minimize the total number of control steps. A number of DSP benchmark circuits have been used to test the proposed algorithm. Depending on the tightness of the resource constraints, significant power reduction can be achieved (an average of 20% and 60% power reduction for tight and loose resource constraints, respectively).