Low-power architectural synthesis and the impact of exploiting locality

Exploiting regularity for low-power design

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Low power high level synthesis by increasing data correlation

ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design

The impact of data characteristics and hardware topology on hardware selection for low power DSP

ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design

System-level power optimization: techniques and tools

ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design

Reducing bus transition activity by limited weight coding with codeword slimming

GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI

A Clustering Approach to Explore Grain-Sizes in the Definitionof Processing Elements in Dataflow Architectures

Journal of VLSI Signal Processing Systems - Special issue on the 1997 IEEE workshop on signal processing systems (SiPS): design and implementation

System-level power optimization: techniques and tools

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Power minimization of functional units partially guarded computation

ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design

Synthesis of low power folded programmable coefficient FIR digital filters (short paper)

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference

Data transmission over a bus with peak-limited transition activity

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference

Interconnect-aware high-level synthesis for low power

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Low-power VLSI synthesis of DSP systems

Integration, the VLSI Journal

Binding, Allocation and Floorplanning in Low Power High-Level Synthesis

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

A High-level Interconnect Power Model for Design Space Exploration

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Incremental exploration of the combined physical and behavioral design space

Proceedings of the 42nd annual Design Automation Conference

Scheduling and Partitioning Schemes for Low Power Designs Using Multiple Supply Voltages

The Journal of Supercomputing

Scheduling and optimal voltage selection with multiple supply voltages under resource constraints

Integration, the VLSI Journal

Multiple voltage synthesis scheme for low power design under timing and resource constraints

Integrated Computer-Aided Engineering

Compatibility path based binding algorithm for interconnect reduction in high level synthesis

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Power optimization for simultaneous scheduling and partitioning with multiple voltages

MMACTE'05 Proceedings of the 7th WSEAS International Conference on Mathematical Methods and Computational Techniques In Electrical Engineering