The impact of data characteristics and hardware topology on hardware selection for low power DSP

Authors:
Gareth Keane;Jonathan Spanier;Roger Woods
Affiliations:
School of Electrical Engineering and Computer Science, The Queen's University of Belfast, Ashby Building, Stranmillis Road, Belfast BT9 5AH, Northern Ireland;School of Electrical Engineering and Computer Science, The Queen's University of Belfast, Ashby Building, Stranmillis Road, Belfast BT9 5AH, Northern Ireland;School of Electrical Engineering and Computer Science, The Queen's University of Belfast, Ashby Building, Stranmillis Road, Belfast BT9 5AH, Northern Ireland
Venue:
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Year:
1998

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Abstract

Adders and multipliers are key operations in DSP systems. The power consumption of adders is well understood but there are few detailed results on the choice of multipliers available. This paper considers how the power consumption of a number of multiplier structures such as Carry-Save array and Wallace Tree multipliers varies with data wordlengths and different layout strategies. In all cases, results were obtained from EPIC PowerMill™ simulations of actual synthesised circuit layouts. Analysis of the results highlights the effects of routing and interconnect optimization for low power operation and gives clear indications on choice of multiplier structure and design flow for the rapid design of DSP systems.