VLSI implementation of discrete wavelet transform
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Multirate Digital Signal Processing: Multirate Systems, Filter Banks, Wavelets
Multirate Digital Signal Processing: Multirate Systems, Filter Banks, Wavelets
Quick-Turnaround ASIC Design in VHDL: Core-Based Behavioral Synthesis
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ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 1 - Volume 1
Issues in wireless video coding using run-time-reconfigurable FPGAs
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Rapid design of discrete orthonormal wavelet transforms using silicon IP components
ICASSP '99 Proceedings of the Acoustics, Speech, and Signal Processing, 1999. on 1999 IEEE International Conference - Volume 04
Symmetry exploitation in digital interpolators/decimators
IEEE Transactions on Signal Processing
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A methodology for rapid silicon design of biorthogonal wavelet transform systems has been developed. This is based on generic, scalable architectures for the forward and inverse wavelet filters. These architectures offer efficient hardware utilisation by combining the linear phase property of biorthogonal filters with decimation and interpolation. The resulting designs have been parameterised in terms of types of wavelet and wordlengths for data and coefficients. Control circuitry is embedded within these cores that allows them to be cascaded for any desired level of decomposition without any interface logic. The time to produce silicon designs for a biorthogonal wavelet system is only the time required to run synthesis and layout tools with no further design effort required. The resulting silicon cores produced are comparable in area and performance to hand-crafted designs. These designs are also portable across a range of foundries and are suitable for FPGA and PLD implementations.