Proceedings of the conference on Design, automation and test in Europe
VLSI architecture for lossless compression of medical images using the discrete wavelet transform
Proceedings of the conference on Design, automation and test in Europe
A nonseparable VLSI architecture for two-dimensional discrete periodized wavelet transform
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Programmable Parallel VLSI Architecture for 2-D Discrete Wavelet Transform
Journal of VLSI Signal Processing Systems - Parallel VLSI architectures for image and video processing
Design of Silicon IP Cores for Biorthogonal Wavelet Transforms
Journal of VLSI Signal Processing Systems - Special issue on signal processing systems design and implementation
An Integrated Systolic Array Design for Video Compression
Journal of VLSI Signal Processing Systems
An Efficient VLSI Architecture for the Computation of 1-D Discrete Wavelet Transform
Journal of VLSI Signal Processing Systems
ICCS '01 Proceedings of the International Conference on Computational Sciences-Part I
Parallel FPGA Implementation of the Split and Merge Discrete Wavelet Transform
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations
Journal of VLSI Signal Processing Systems
Discrete Wavelet Transform: Architectures, Design and Performance Issues
Journal of VLSI Signal Processing Systems
Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT
Journal of VLSI Signal Processing Systems
VLSI Implementation for One-Dimensional Multilevel Lifting-Based Wavelet Transform
IEEE Transactions on Computers
Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current
Journal of Electronic Testing: Theory and Applications
Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of VLSI Signal Processing Systems
A Novel FPGA Architecture of a 2-D Wavelet Transform
Journal of VLSI Signal Processing Systems
A novel VLSI architecture for real-time line-based wavelet transform using lifting scheme
Journal of Computer Science and Technology
An Efficient Wavelet Based Feature Extraction Method for Face Recognition
ISNN 2009 Proceedings of the 6th International Symposium on Neural Networks: Advances in Neural Networks - Part III
Memory reduction methodology for distributed-arithmetic- based DWT/IDWT exploiting data symmetry
IEEE Transactions on Circuits and Systems II: Express Briefs
A robust wavelet based feature extraction method for face recognition
SMC'09 Proceedings of the 2009 IEEE international conference on Systems, Man and Cybernetics
A pipeline VLSI architecture for high-speed computation of the 1-D discrete wavelet transform
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Optimized hardware implementation for tile-based convolutional 2-D discrete wavelet transform
ICS'06 Proceedings of the 10th WSEAS international conference on Systems
FPGA discrete wavelet transform encoder/decoder implementation
ICONIP'06 Proceedings of the 13th international conference on Neural information processing - Volume Part III
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This paper presents a VLSI implementation of discrete wavelet transform (DWT). The architecture is simple, modular, and cascadable for computation of one or multidimensional DWT. It comprises of four basic units: input delay, filter, register bank, and control unit. The proposed architecture is systolic in nature and performs both high- and low-pass coefficient calculations with only one set of multipliers. In addition, it requires a small on-chip interface circuitry for interconnection to a standard communication bus. A detailed analysis of the effect of finite precision of data and wavelet filter coefficients on the accuracy of the DWT coefficients is presented. The architecture has been simulated in VLSI and has a hardware utilization efficiency of 87.5%. Being systolic in nature, the architecture can compute DWT at a data rate of N/spl times/10/sup 6/ samples/s corresponding to a clock speed of N MHz.