Optimized hardware implementation for tile-based convolutional 2-D discrete wavelet transform

Authors:
Gregory Dimitroulakos;Michalis D. Galanis;Costas E. Goutis
Affiliations:
VLSI Design Lab., Electrical and Computer Engineering Department, University of Patras, Patras, Greece;VLSI Design Lab., Electrical and Computer Engineering Department, University of Patras, Patras, Greece;VLSI Design Lab., Electrical and Computer Engineering Department, University of Patras, Patras, Greece
Venue:
ICS'06 Proceedings of the 10th WSEAS international conference on Systems
Year:
2006

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Abstract

The design and implementation of an efficient hardware architecture in terms of speed and memory requirements for computing the tile-based Two-Dimensional Forward Discrete Wavelet Transform for the JPEG2000 still image compression standard, is described in this paper. This architecture is derived from a well-established architecture template for calculating the Two-Dimensional Forward Discrete Wavelet Transform. The filters of that template are replaced by our previously published throughput-optimized ones. A proper scheduling algorithm has been developed that it matches to the special features of our filtering units. The performance improvements are due to the throughput-optimized filters. Also, due to the developed scheduling algorithm, reduced memory requirements are achieved when compared with previously published architectures.