An efficient architecture for lifting-based two-dimensional discrete wavelet transforms
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Journal of VLSI Signal Processing Systems
An efficient architecture for lifting-based two-dimensional discrete wavelet transforms
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
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An efficient architecture for lifting-based two-dimensional discrete wavelet transforms
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In this paper, the three main hardware architectures for the 2-D discrete wavelet transform (2-D-DWT) are reviewed. Also, optimization techniques applicable to all three architectures are described. The main contribution of this work is the quantitative comparison among these design alternatives for the 2-D-DWT. The comparison is performed in terms of memory requirements, throughput, and energy dissipation, and is based on a theoretical analysis of the alternative architectures and schedules. Memory requirements, throughput, and energy are expressed by analytical equations with parameters from both the 2-D-DWT algorithm and the implementation platform. The parameterized equations enable the early but efficient exploration of the various tradeoffs related to the selection to the one or the other architecture