A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
JPEG 2000: Image Compression Fundamentals, Standards and Practice
JPEG 2000: Image Compression Fundamentals, Standards and Practice
Implementation of the JPEG 2000 Standard on a Virtex 1000 FPGA
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Reconfigurable Hardware Implementations for Lifting-Based DWT Image Processing Algorithms
ICESS '08 Proceedings of the 2008 International Conference on Embedded Software and Systems
Computers and Electrical Engineering
Multi-focus image fusion for visual sensor networks in DCT domain
Computers and Electrical Engineering
A VLSI architecture for lifting-based forward and inverse wavelettransform
IEEE Transactions on Signal Processing
Low-power and high-speed VLSI architecture for lifting-based forward and inverse wavelet transform
IEEE Transactions on Consumer Electronics
The JPEG still picture compression standard
IEEE Transactions on Consumer Electronics
IEEE Transactions on Consumer Electronics
Evaluation of design alternatives for the 2-D-discrete wavelet transform
IEEE Transactions on Circuits and Systems for Video Technology
Combined line-based architecture for the 5-3 and 9-7 wavelet transform of JPEG2000
IEEE Transactions on Circuits and Systems for Video Technology
Computer Networks: The International Journal of Computer and Telecommunications Networking
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A resource efficient and high-performance architecture for a two-dimensional multi-level discrete wavelet transform processor is presented in this paper. The JPEG2000 standard integer lossless 5-3 filter has been implemented. It achieves optimal hardware utilisation with minimal combinational logic block slices and high frequency of operation. To reduce the hardware complexity and to achieve high performance the proposed architecture implements lifting scheme with a single multiplier-free processing element to perform both predict and update operations. Symmetric extension is used at image boundaries without requiring any extra clock cycle. The generic architecture is very flexible and can perform up to five levels of forward transform on any arbitrary image size. Synthesis of the 5-level architecture on Xilinx Virtex 5 FPGA shows that the processor can achieve a maximum frequency of operation of 221.44MHz. The reduced hardware complexity and high frequency of operation render the design suitable for incorporation in image processing applications requiring fast operations. The 5-level design has been successfully implemented on a Xilinx Spartan 3E FPGA, utilising only 1104 slices for a 512-by-512 pixel test image, the lowest hardware requirements for a 5-level discrete wavelet transform processor reported to date.