The JPEG still picture compression standard
Communications of the ACM - Special issue on digital multimedia systems
Ten lectures on wavelets
Wavelets and subband coding
Implementation of the JPEG 2000 Standard on a Virtex 1000 FPGA
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Multiplierless modules for forward and backward integer wavelet transform
CompSysTech '03 Proceedings of the 4th international conference conference on Computer systems and technologies: e-Learning
A real-time wavelet-domain video denoising implementation in FPGA
EURASIP Journal on Embedded Systems
Design and FPGA implementation of lifting scheme for 2D-DWT using wavepipelining
ISCGAV'05 Proceedings of the 5th WSEAS International Conference on Signal Processing, Computational Geometry & Artificial Vision
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Design and implementation of a modified SPIHT algorithm for image compression
ISC '07 Proceedings of the 10th IASTED International Conference on Intelligent Systems and Control
Poly-DWT: Polymorphic wavelet hardware support for dynamic image compression
ACM Transactions on Embedded Computing Systems (TECS)
Efficient parallel architecture for multi-level forward discrete wavelet transform processors
Computers and Electrical Engineering
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Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression \cite{TenLectures, Shapiro, Spiht}. However, the algorithms proposed in literature assume random access to the whole image. This makes the algorithms unsuitable for hardware solutions because of extensive access to external memory. Here, we present an efficient architecture for computing DWT of images, which is based on a partitioned approach for lossy image compression~\cite{Ritter}. The architecture achieves its computational power by using pipelining and taking advantage of the flexible memory configurations available in FPGA's.