Wavelets and subband coding
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Line Based, Reduced Memory, Wavelet Image Compression
DCC '98 Proceedings of the Conference on Data Compression
Design and Implementation of a Generic 2-D Orthogonal Discrete Wavelet Transform on FPGA
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Automated Least-Significant Bit Datapath Optimization for FPGAs
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Smart Camera Based on Reconfigurable Hardware Enables Diverse Real-Time Applications
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Design and Implementation of a Generic 2-D Biorthogonal Discrete Wavelet Transform on an FPGA
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
FreePDK: An Open-Source Variation-Aware Design Kit
MSE '07 Proceedings of the 2007 IEEE International Conference on Microelectronic Systems Education
Auto-adaptive reconfigurable architecture for scalable multimedia applications
AHS '07 Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems
Fusion of thermal infrared and visible spectrum video for robust surveillance
ICVGIP'06 Proceedings of the 5th Indian conference on Computer Vision, Graphics and Image Processing
Scalable, Wavelet-Based Video: From Server to Hardware-Accelerated Client
IEEE Transactions on Multimedia
The JPEG2000 still image coding system: an overview
IEEE Transactions on Consumer Electronics
An image multiresolution representation for lossless and lossy compression
IEEE Transactions on Image Processing
Motion-compensated 3-D subband coding of video
IEEE Transactions on Image Processing
High performance scalable image compression with EBCOT
IEEE Transactions on Image Processing
Wavelet filter evaluation for image compression
IEEE Transactions on Image Processing
Rationalizing the coefficients of popular biorthogonal wavelet filters
IEEE Transactions on Circuits and Systems for Video Technology
Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000
IEEE Transactions on Circuits and Systems for Video Technology
SPIHT image compression on FPGAs
IEEE Transactions on Circuits and Systems for Video Technology
4-D Wavelet-Based Multiview Video Coding
IEEE Transactions on Circuits and Systems for Video Technology
Overview of the Scalable Video Coding Extension of the H.264/AVC Standard
IEEE Transactions on Circuits and Systems for Video Technology
Efficient compression and network adaptive video coding for distributed video surveillance
Multimedia Tools and Applications
Journal of Real-Time Image Processing
Efficient health data compression on mobile devices
Proceedings of the 3rd ACM MobiHoc workshop on Pervasive wireless healthcare
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Many modern computing applications have been enabled through the use of real-time multimedia processing. While several hardware architectures have been proposed in the research literature to support such primitives, these fail to address applications whose performance and resource requirements have a dynamic aspect. Embedded multimedia systems typically need a power and computation efficient design in addition to good compression performance. In this article, we introduce a Polymorphic Wavelet Architecture (Poly-DWT) as a crucial building block towards the development of embedded systems to address such challenges. We illustrate how our Poly-DWT architecture can potentially make dynamic resource allocation decisions, such as the internal bit representation and the processing kernel, according to the application requirements. We introduce a filter switching architecture that allows for dynamic switching between 5/3 and 9/7 wavelet filters and leads to a more power efficient design. Further, a multiplier-free design with a low adder requirement demonstrates the potential of Poly-DWT for embedded systems. Through an FPGA prototype, we perform a quantitative analysis of our Poly-DWT architecture, and compare our filter to existing approaches to illustrate the area and performance benefits inherent in our approach.