A proposal for a new block encryption standard
EUROCRYPT '90 Proceedings of the workshop on the theory and application of cryptographic techniques on Advances in cryptology
Comparison of Several Wavelet Coefficient Confusion Methods Applied in Multimedia Encryption
ICCNMC '03 Proceedings of the 2003 International Conference on Computer Networks and Mobile Computing
Key-dependency for a wavelet-based blind watermarking algorithm
Proceedings of the 2004 workshop on Multimedia and security
A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Parameterized biorthogonal wavelet lifting for lightweight JPEG 2000 transparent encryption
MM&Sec '05 Proceedings of the 7th workshop on Multimedia and security
Digital Design (4th Edition)
FreePDK: An Open-Source Variation-Aware Design Kit
MSE '07 Proceedings of the 2007 IEEE International Conference on Microelectronic Systems Education
Analysis of the SSL 3.0 protocol
WOEC'96 Proceedings of the 2nd conference on Proceedings of the Second USENIX Workshop on Electronic Commerce - Volume 2
Security Cryptanalysis in High-Order Improved Fast Encryption Algorithm for Multimedia
FGCN '07 Proceedings of the Future Generation Communication and Networking - Volume 01
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
Multimode embedded compression codec engine for power-aware video coding system
IEEE Transactions on Circuits and Systems for Video Technology
A Reconfigurable Architecture for Secure Multimedia Delivery
VLSID '10 Proceedings of the 2010 23rd International Conference on VLSI Design
The effect of LUT and cluster size on deep-submicron FPGA performance and density
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
Poly-DWT: Polymorphic wavelet hardware support for dynamic image compression
ACM Transactions on Embedded Computing Systems (TECS)
Partial encryption of compressed images and videos
IEEE Transactions on Signal Processing
Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform
IEEE Transactions on Signal Processing
IEEE Transactions on Signal Processing
Multimedia Selective Encryption by Means of Randomized Arithmetic Coding
IEEE Transactions on Multimedia
Fast encryption for multimedia
IEEE Transactions on Consumer Electronics
The JPEG2000 still image coding system: an overview
IEEE Transactions on Consumer Electronics
A joint signal processing and cryptographic approach to multimedia encryption
IEEE Transactions on Image Processing
Commutative Encryption and Watermarking in Video Compression
IEEE Transactions on Circuits and Systems for Video Technology
Privacy Protected Surveillance Using Secure Visual Object Coding
IEEE Transactions on Circuits and Systems for Video Technology
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There has been an increasing concern for the security of multimedia transactions over real-time embedded systems. Partial and selective encryption schemes have been proposed in the research literature, but these schemes significantly increase the computation cost leading to tradeoffs in system latency, throughput, hardware requirements and power usage. In this paper, we propose a light-weight multimedia encryption strategy based on a modified discrete wavelet transform (DWT) which we refer to as the secure wavelet transform (SWT). The SWT provides joint multimedia encryption and compression by two modifications over the traditional DWT implementations: (a) parameterized construction of the DWT and (b) subband re-orientation for the wavelet decomposition. The SWT has rational coefficients which allow us to build a high throughput hardware implementation on fixed point arithmetic. We obtain a zero-overhead implementation on custom hardware. Furthermore, a Look-up table based reconfigurable implementation allows us to allocate the encryption key to the hardware at run-time. Direct implementation on Xilinx Virtex FPGA gave a clock frequency of 60 MHz while a reconfigurable multiplier based design gave a improved clock frequency of 114 MHz. The pipelined implementation of the SWT achieved a clock frequency of 240 MHz on a Xilinx Virtex-4 FPGA and met the timing constraint of 500 MHz on a standard cell realization using 45 nm CMOS technology.