Design and Implementation of a Generic 2-D Orthogonal Discrete Wavelet Transform on FPGA

• Authors: A Benkrid;K Benkrid;D. Crookes
• Venue: FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
• Year: 2003

This paper gives a design framework for the implementation ofthe 2-D Orthogonal Discrete Wavelet Transform (DWT) onFPGA. The architecture is based on the Pyramid AlgorithmAnalysis. It maps spatially the multistage filter banks of theDWT on Xilinx Virtex-e FPGA family using on chip buffering.The architecture takes advantage from the low rate of the hightransform stages to reuse the logic. In this paper, we proposea novel FIR structure to handle the computation along theborders using symmetry extension, a new BlockRamconfiguration for multi ports shift register, and a newmathematical approach to predict and reduce the errordynamic range due to wordlength rounding. For an MxMimage size input, our architecture has a period of M2 clockcycles, and requires the minimum storage size. Thearchitecture is highly scalable for different filter lengths andnumber of octaves. The implementation results for a specific2-D Daubechies-4 Wavelet transform are included.