Generic systolic array for run-time scalable cores
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
Poly-DWT: Polymorphic wavelet hardware support for dynamic image compression
ACM Transactions on Embedded Computing Systems (TECS)
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The paper presents a layered reconfigurable architecture based on partial and dynamical reconfigurable FPGA in order to meet the adaptivity and scalability needs in multimedia applications. An efficient adaptivity is enabled thanks to the introduction of an application adaptive level and a task adaptive level organisation. This organisation is materialized through a global hardware reconfiguration and local hardware reconfiguration by using partial and dynamic reconfiguration of FPGAs. A case study of a discret wavelet transform is used to demonstrate the feasibility in task adaptive level considering different types of filters. A platform based on a Xilinx Virtex-4 FPGA is used for experimental implementation.