A scalable architecture for discrete wavelet transform
CAMP '95 Proceedings of the Computer Architectures for Machine Perception
Reconfigurable Shape-Adaptive Template Matching Architectures
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Distributed arithmetic FPGA design with online scalable size and performance
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
FPGA-Based Customizable Systolic Architecture for Image Processing Applications
RECONFIG '05 Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05) on Reconfigurable Computing and FPGAs
Scalable reconfigurable channel decoder architecture for future wireless handsets
Proceedings of the conference on Design, automation and test in Europe
Auto-adaptive reconfigurable architecture for scalable multimedia applications
AHS '07 Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic
IEEE Transactions on Signal Processing - Part I
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This paper presents a scalable core architecture based on a generic systolic array. The size of this kind of cores can be adapted in real-time to cover changing application requirements or to the available area in a reconfigurable device. In this paper, the process of scaling the core is performed by the replication of a single processing element using run-time partial reconfiguration. Furthermore, rather than restricting the proposed solution to a given application, it is based on a generic systolic architecture which is adapted using a design flow which is also proposed. The paper includes a related work discussion, the proposal and definition of a systolic array communication approach, which does not require the use of specific macro structures and permits to achieve higher flexibility, and a design flow used to adapt the generic architecture. Further, the paper also includes an image filter application as a simple use case, along with implementation results for Virtex 5 FPGA.