Distributed arithmetic FPGA design with online scalable size and performance

Authors:
Klaus Danne
Affiliations:
University of Paderborn, Paderborn, Germany
Venue:
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Year:
2004

Citing 4
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Abstract

The partial runtime reconfiguration capability of FPGAs allows task execution in a multitasking manner. In contrasts to most other models, we assume that each task has several implementation variants with different performance and size. Moreover, one task variant is an extension of another. Therefore, a task can change between its variants without reconfiguring the entire task footprint. As case study, we introduce an online scalable distributed arithmetic design and review the advantages.