Partitioning Processor Arrays under Resource Constraints
Journal of VLSI Signal Processing Systems
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Run-time compaction of FPGA designs
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
A New Exact Algorithm for General Orthogonal D-Dimensional Knapsack Problems
ESA '97 Proceedings of the 5th Annual European Symposium on Algorithms
Processor Allocation in k-ary n-cube Multiprocessors
ISPAN '97 Proceedings of the 1997 International Symposium on Parallel Architectures, Algorithms and Networks
Algorithmic Graph Theory and Perfect Graphs (Annals of Discrete Mathematics, Vol 57)
Algorithmic Graph Theory and Perfect Graphs (Annals of Discrete Mathematics, Vol 57)
Optimal FPGA module placement with temporal precedence constraints
Proceedings of the conference on Design, automation and test in Europe
Higher-Dimensional Packing with Order Constraints
WADS '01 Proceedings of the 7th International Workshop on Algorithms and Data Structures
The Journal of Supercomputing
Distributed arithmetic FPGA design with online scalable size and performance
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Temporal floorplanning using the T-tree formulation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An EDF schedulability test for periodic tasks on reconfigurable hardware devices
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
Offline and online aspects of defragmenting the module layout of a partially reconfigurable device
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ReconOS: Multithreaded programming for reconfigurable computers
ACM Transactions on Embedded Computing Systems (TECS)
Partitioned scheduling of periodic real-time tasks onto reconfigurable hardware
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
New three-level resource management enhancing quality of offline hardware task placement on FPGA
International Journal of Reconfigurable Computing
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Recent generations of Field Programmable Gate Arrays (FPGA) allow the dynamic reconfiguration of cells on the chip during run-time. For a given problem consisting of a set of tasks with computation requirements modeled by rectangles of cells, several optimization problems such as finding the array of minimal size to accomplish the tasks within a given time limit are considered. Existing approaches based on ILP formulations to solve these problems as multi-dimensional packing problems turn out not to be applicable for problem sizes of interest. Here, a breakthrough is achieved in solving these problems to optimality by using the new notion of packing classes. It allows a significant reduction of the search space such that problems of the above type may be solved exactly using a special branch-and-bound technique. We validate the usefulness of our method by providing computational results.