Dynamic Reconfiguration to Support Concurrent Applications
IEEE Transactions on Computers
Configuration relocation and defragmentation for run-time reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimization of Dynamic Hardware Reconfigurations
The Journal of Supercomputing
Fast Template Placement for Reconfigurable Computing Systems
IEEE Design & Test
Run-Time Management of Dynamically Recongigurable Designs
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
A Hardwar Operating System for Dynamic Reconfiguration of FPGAs
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
A Virtual Hardware Operating System for the Xilinx XC6200
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
The swappable logic unit: a paradigm for virtual hardware
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
A dynamic reconfiguration run-time system
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Designing an Operating System for a Heterogeneous Reconfigurable SoC
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks
IEEE Transactions on Computers
Seamless Hardware-Software Integration in Reconfigurable Computing Systems
IEEE Design & Test
The Development of an Operating System for Reconfigurable Computing
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
FIFO Communication Models in Operating Systems for Reconfigurable Computing
FCCM '05 Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
An EDF schedulability test for periodic tasks on reconfigurable hardware devices
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
Computer
Run-Time Services for Hybrid CPU/FPGA Systems on Chip
RTSS '06 Proceedings of the 27th IEEE International Real-Time Systems Symposium
Real-Time Management of Hardware and Software Tasks for FPGA-based Embedded Systems
IEEE Transactions on Computers
Design and architectures for dependable embedded systems
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
FlexTiles: self adaptive heterogeneous manycore based on flexible tiles (FP7 project)
Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop
Chameleon: operating system support for dynamic processors
ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
Multithreading on reconfigurable hardware: An architectural approach
Microprocessors & Microsystems
Dynamic objects: Supporting fast and easy run-time reconfiguration in FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
A self-adaptive heterogeneous multi-core architecture for embedded real-time video object tracking
Journal of Real-Time Image Processing
A low overhead abstract architecture for FPGA resource management
ACM SIGARCH Computer Architecture News - ACM SIGARCH Computer Architecture News/HEART '12
Self-adaptive on-chip system based on cross-layer adaptation approach
International Journal of Reconfigurable Computing
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Rising logic densities together with the inclusion of dedicated processor cores push reconfigurable devices from being applied for glue logic and prototyping towards implementing complete reconfigurable systems-on-chip. The mix of fast CPU cores and fine-grained reconfigurable logic allows to map both sequential, control-dominated code and highly parallel data-centric computations onto one platform. However, traditional design techniques that view specialized hardware circuits as passive coprocessors are ill-suited for programming these reconfigurable computers. In particular, the programming models for software—running on an embedded operating system—and digital hardware—synthesized to an FPGA—lack commonalities, which hinders design space exploration and severely impairs the potential for code reuse. In this article, we present ReconOS, an execution environment based on existing embedded operating systems that extends the multithreaded programming model established in the software domain to reconfigurable hardware. Using threads and common synchronization and communication services as an abstraction layer, ReconOS allows for the creation of portable and flexible multithreaded applications targeting CPU/FPGA systems. This article discusses the ReconOS programming model and its execution environment, presents implementations based on modern platform FPGAs and the operating systems eCos and Linux, evaluates time and area overheads of the proposed mechanisms and, finally, demonstrates the feasibility of the multithreading design approach on several case studies.