Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Proceedings of the 39th annual Design Automation Conference
Real-Time Design Patterns: Robust Scalable Architecture for Real-Time Systems
Real-Time Design Patterns: Robust Scalable Architecture for Real-Time Systems
Preemptive Multitasking on FPGAs
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Run-time support for dynamically reconfigurable computing systems
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
A Lightweight Approach for Embedded Reconfiguration of FPGAs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks
IEEE Transactions on Computers
Model Reuse through Hardware Design Patterns
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Seamless Hardware-Software Integration in Reconfigurable Computing Systems
IEEE Design & Test
Dynamic Hardware Multiplexing: Improving Adaptability with a Run Time Reconfiguration Manager
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
REPLICA2Pro: task relocation by bitstream manipulation in virtex-II/Pro FPGAs
Proceedings of the 3rd conference on Computing frontiers
Efficient hardware checkpointing: concepts, overhead analysis, and implementation
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
OOCE: Object-Oriented Communication Engine for SoC Design
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Real-Time Management of Hardware and Software Tasks for FPGA-based Embedded Systems
IEEE Transactions on Computers
A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH
ACM Transactions on Embedded Computing Systems (TECS)
ReconOS: Multithreaded programming for reconfigurable computers
ACM Transactions on Embedded Computing Systems (TECS)
Virtual Configuration Management: A Technique for Partial Runtime Reconfiguration
IEEE Transactions on Computers
VAPRES: a virtual architecture for partially reconfigurable embedded systems
Proceedings of the Conference on Design, Automation and Test in Europe
Bitstream relocation with local clock domains for partially reconfigurable FPGAs
Proceedings of the Conference on Design, Automation and Test in Europe
Journal of Systems Architecture: the EUROMICRO Journal
Persistence Management Model for Dynamically Reconfigurable Hardware
DSD '10 Proceedings of the 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
Hardware supported task scheduling on dynamically reconfigurable SoC architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware OS Communication Service and Dynamic Memory Management for RSoCs
RECONFIG '11 Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs
Hardware Resource Virtualization for Dynamically Partially Reconfigurable Systems
IEEE Embedded Systems Letters
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Partial reconfiguration capabilities must be exploited to obtain the maximum benefits from dynamically reconfigurable FPGAs. Partial reconfiguration process management still faces a set of open problems that have thus far made it impossible to take full advantage of partial and dynamic reconfiguration. The work presented in this article proposes a novel architecture, development workflow, and modelling approach for dynamically reconfigurable systems management using an object model that offers a global solution. This solution is built on a system-level middleware that provides the infrastructure and tools for communication between different components in heterogeneous embedded systems. Several experiments were performed to test and evaluate each part of our proposed solution, and the obtained results are presented. These results demonstrate the excellent performance of our proposed solution.