The Unified Modeling Language user guide
The Unified Modeling Language user guide
Dynamically reconfigurable architecture for image processor applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
A Framework for Run-time Reconfigurable Systems
The Journal of Supercomputing
Configuration relocation and defragmentation for run-time reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Guest Editors' Introduction: Configurable Computing
IEEE Design & Test
An Evaluation of an FPGA Run-Time Support System
DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
JHDL - An HDL for Reconfigurable Systems
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
A reconfigurable computing platform for real time embedded applications
Microprocessors & Microsystems
A dynamically reconfigurable communication architecture for multicore embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
Dynamic objects: Supporting fast and easy run-time reconfiguration in FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
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Reconfigurable computing systems normally consist of an instruction-set processor connected to a block of reconfigurable logic. The reconfigurable logic, for example, an field programmable gate arrays (FPGA), can usually be adapted during the run-time of an application to perform different tasks. This paper describes a novel FPGA support system (FSS) that facilitates the execution of hardware-based tasks on a reconfigurable Xilinx 6264 FPGA connected to an ARM 7 processor. The FSS provides the mechanisms to support the placement, execution, and removal of tasks on the FPGA. A key feature of the FSS is the ability to provide communication facilities between concurrently active hardware and software tasks during the run-time of an application. The design, implementation and status of the FSS are discussed, together with initial results based on the implementation of a wavelet image compression application. The paper concludes by considering how our experiences with this system have influenced the development of an enhanced FSS for the later generation of Xilinx Virtex FPGAs.