Run-time support for dynamically reconfigurable computing systems
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
Platform-independent methodology for partial reconfiguration
Proceedings of the 1st conference on Computing frontiers
Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
A Novel Approach to Minimizing Reconfiguration Cost for LUT-Based FPGAs
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Configuration Compression for Virtex FPGAs
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Application-specific network-on-chip architecture customization via long-range link insertion
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A methodology for mapping multiple use-cases onto networks on chips
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Support for partial run-time reconfiguration of platform FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
A New Placement Approach to Minimizing FPGA Reconfiguration Data
ICESS '08 Proceedings of the 2008 International Conference on Embedded Software and Systems
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
Partial Reconfiguration Bitstream Compression for Virtex FPGAs
CISP '08 Proceedings of the 2008 Congress on Image and Signal Processing, Vol. 5 - Volume 05
Virtual point-to-point connections for NoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Efficient architectures for 3D HWT using dynamic partial reconfiguration
Journal of Systems Architecture: the EUROMICRO Journal
Automatically mapping applications to a self-reconfiguring platform
Proceedings of the Conference on Design, Automation and Test in Europe
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Dynamic Reconfigurable Networks in NoC for I/O Supported Parallel Applications
CIT '10 Proceedings of the 2010 10th IEEE International Conference on Computer and Information Technology
A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier
FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
Skip the Analysis: Self-Optimising Networks-on-Chip (Invited Paper)
ISED '10 Proceedings of the 2010 International Symposium on Electronic System Design
Configuration compression for FPGA-based embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Application-Aware Topology Reconfiguration for On-Chip Networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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To deal with the communication bottleneck of multiprocessor systems, several communication architectures have been proposed in the last decade. Yet, none of them has demonstrated the performance of the direct connections between two communicating units. In this paper, we propose dynamically reconfigurable point-to-point (DRP2P) interconnects for setting up direct connection between two communicating units before the communication starts. DRP2P is neither point-to-point (P2P) nor Network-on-Chip (NoC); it stands between these two on-chip communication architectures. It is as fast as P2P and as scalable as NoC. Instead of using routers like in NoC, we utilize partial reconfiguration ability of FPGAs for routing data packets. Furthermore, DRP2P can work both on regular and irregular topologies. The only drawback of our approach is the reconfiguration latency. This drawback is completely hidden when the reconfiguration of the communication links is achieved during the computation times of the cores. DRP2P solves the scalability issue of P2P by setting up on-demand communication-specific links between cores. So, the occupied area and the total power consumption of communication architecture can be reduced significantly. We designed an on-chip self-reconfiguration core, c^2PCAP so as to achieve DRP2P interconnects as fast as possible. The c^2PCAP core is designed for Xilinx FPGAs and can partially reconfigure the FPGA at the highest rate proposed by the manufacturer (e.g. up to 400MB/s for Virtex-4).