FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
An optimal algorithm for minimizing run-time reconfiguration delay
ACM Transactions on Embedded Computing Systems (TECS)
A Reconfiguration Manager for Dynamically Reconfigurable Hardware
IEEE Design & Test
Configuration bitstream compression for dynamically reconfigurable FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Optimal reconfiguration sequence management
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A new approach to compress the configuration information of programmable devices
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
A new decompression system for the configuration process of SRAM-based FPGAS
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Reconfiguration in network of embedded systems: Challenges and adaptive tracking case study
Journal of Embedded Computing - Real-Time and Embedded Computing Systems
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
IEICE - Transactions on Information and Systems
Hardware Decompression Techniques for FPGA-Based Embedded Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
International Journal of Reconfigurable Computing - Selected papers from ReCoSoc08
A cost-effective context memory structure for dynamically reconfigurable processors
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
A configuration memory hierarchy for fast reconfiguration with reduced energy consumption overhead
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Configuration compression for FPGA-based embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test compression for dynamically reconfigurable processors
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Updating directed minimum cost spanning trees
WEA'06 Proceedings of the 5th international conference on Experimental Algorithms
A configuration system architecture supporting bit-stream compression for FPGAs
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
A cost model for partial dynamic reconfiguration
Transactions on High-Performance Embedded Architectures and Compilers IV
A dynamically reconfigurable communication architecture for multicore embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
Improving bitstream compression by modifying FPGA architecture
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
FPGA bitstream compression and decompression using LZ and golomb coding (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Computers and Electrical Engineering
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Although run-time reconfigurable systems have been shown to achieve very high performance, the speedups over traditional microprocessor systems are limited by the cost of configuration of the hardware. Current reconfigurable systems suffer from a significant overhead due to the time it takes to reconfigure their hardware. In order to deal with this overhead, and increase the compute power of reconfigurable systems, it is important to develop hardware and software systems to reduce or eliminate this delay. In this paper, we explore the idea of configuration compression and develop algorithms for reconfigurable systems. These algorithms, targeted to Xilinx Virtex series FPGAs with minimum modification of hardware, can significantly reduce the amount of data needed to transfer during configuration. In this work we have extensively researched the current compression techniques, including the Huffman coding, the Arithmetic coding and LZ coding. We have also developed different algorithms targeting different hardware structures. Our readback algorithm allows certain frames to be reused as a dictionary and sufficiently utilize the regularities within the configuration bitstream. In addition, we have developed frame reordering techniques that better uses the regularities by shuffling the sequence of the configuration. We have also developed the wildcard approach that can be used for true partial reconfiguration. The simulation results demonstrate that a factor of 4 compression ratio can be achieved.