ACM Transactions on Information Systems (TOIS)
Configuration compression for FPGA-based embedded systems
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Configuration Compression for Virtex FPGAs
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Configuration bitstream compression for dynamically reconfigurable FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Test compression for dynamically reconfigurable processors
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Improving bitstream compression by modifying FPGA architecture
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Dynamically reconfigurable entropy coder for multi-standard video adaptation using FaRM
Microprocessors & Microsystems
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During the last decade programmable devices have gained an impressive diffusion, tackling some traditional ASIC marked domains. In particular, multi-million gate FPGAs have become a very appealing low-cost solution even for consumer applications. However, one of the big issues that can arise with modern FPGA devices is the need for large and expensive external non-volatile memory to keep the configuration data. In this work we developed an alternative technique to compress FPGA bitstreams based on the knowledge of the device internal structure. The proposed method performs a two-step coder: in the first step the bitstream is adaptively "filtered" to remove data redundancy, while in the second step an arithmetic coder is used to actually compress the information. The effectiveness of the proposed technique has been demonstrated on a set of case studies. As a result conventional approaches are out-performed reaching a compression ratio of 4.26 against 3.3 times.