Configuration Compression for Virtex FPGAs
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A new approach to compress the configuration information of programmable devices
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Decoding-aware compression of FPGA bitstreams
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Configuration Bitstream Reduction for SRAM-based FPGAs by Enumerating LUT Input Permutations
RECONFIG '11 Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs
Statistical Analysis and Design of HARP FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The size of configuration bitstreams of field-programmable gate arrays (FPGA) is increasing rapidly. Compression techniques are used to decrease the size of bitstreams. In this paper, an appropriate bitstream format and variable symbol lengths are proposed to utilize the routing patterns for enhancing the compression efficiency. An order of inputs of multiplexers in switch modules is also proposed to improve the symbol statistics and hence, the compression efficiency. A framework to generate the bitstream and hardware description of FPGAs is developed as well. Experimental results over 20 MCNC benchmarks show that by applying the proposed approaches, the compression rate is improved by 46% on average compared to the methods with fixed symbol lengths without any area and performance degradation.