PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Delay-optimal technology mapping for FPGAs with heterogeneous LUTs
DAC '98 Proceedings of the 35th annual Design Automation Conference
Using sparse crossbars within LUT
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
The stratixπ routing and logic architecture
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Architectures and algorithms for field-programmable gate arrays with embedded memory
Architectures and algorithms for field-programmable gate arrays with embedded memory
A detailed power model for field-programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Embedded floating-point units in FPGAs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Area and delay trade-offs in the circuit and architecture design of FPGAs
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Automated transistor sizing for FPGA architecture exploration
Proceedings of the 45th annual Design Automation Conference
The effect of LUT and cluster size on deep-submicron FPGA performance and density
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
Statistical Analysis and Design of HARP FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improvements to Technology Mapping for LUT-Based FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Benchmarking and evaluating reconfigurable architectures targeting the mobile domain
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
FPGA architecture optimisation using geometric programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A decoder-based switch box to mitigate soft errors in SRAM-based FPGAs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Improving FPGA placement with dynamically adaptive stochastic tunneling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Mitigating soft errors in SRAM-based FPGAs by decoding configuration bits in switch boxes
Microelectronics Journal
Exploring area and delay tradeoffs in FPGAs with architecture and automated transistor design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only)
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Towards scalable FPGA CAD through architecture
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Scalable and deterministic timing-driven parallel placement for FPGAs
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only)
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
FPGA placement by graph isomorphism (abstract only)
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Area-efficient FPGA logic elements: architecture and synthesis
Proceedings of the 16th Asia and South Pacific Design Automation Conference
An integer programming placement approach to FPGA clock power reduction
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Efficient and Deterministic Parallel Placement for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Evaluation of FPGA routing architectures under process variation
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Comparison between heterogeneous mesh-based and tree-based application specific FPGA
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
Exploration of heterogeneous FPGA architectures
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
Ultra-fine grain FPGAs: A granularity study
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Parallelization of the channel width search for FPGA routing
ACM SIGARCH Computer Architecture News
Making wide-issue VLIW processors viable on FPGAs
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
Temperature aware statistical static timing analysis
Proceedings of the International Conference on Computer-Aided Design
Mitigating FPGA interconnect soft errors by in-place LUT inversion
Proceedings of the International Conference on Computer-Aided Design
Architecture and performance evaluation of 3D CMOS-NEM FPGA
Proceedings of the System Level Interconnect Prediction Workshop
Limit study of energy & delay benefits of component-specific routing
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Reducing the cost of floating-point mantissa alignment and normalization in FPGAs
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Networked architecture for hybrid electrical energy storage systems
Proceedings of the 49th Annual Design Automation Conference
PDPR: fine-grained placement for dynamic partially reconfigurable FPGAs
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Microprocessors & Microsystems
Fully-functional FPGA prototype with fine-grain programmable body biasing
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Improving bitstream compression by modifying FPGA architecture
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Indirect connection aware attraction for FPGA clustering (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
A novel FPGA design framework with VLSI post-routing performance analysis (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
On supporting rapid exploration of memory hierarchies onto FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
A compiler for scalable placement and routing of brain-like architectures
Proceedings of the 2013 ACM international symposium on International symposium on physical design
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011)
Exploring the use of emerging nonvolatile memory technologies in future FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Towards development of an analytical model relating FPGA architecture parameters to routability
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special Section on 19th Reconfigurable Architectures Workshop (RAW 2012)
Analyzing System-Level Information’s Correlation to FPGA Placement
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Integration, the VLSI Journal
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The VPR toolset [6, 7] has been widely used to perform FPGA architecture and CAD research, but has not evolved over the past decade to include many architectural features now present in modern FPGAs. This paper describes a new version of the toolset that includes four significant features: first, it now supports a broad range of single-driver routing architectures [29, 4, 16]. Single-driver routing has significantly different architectural and electrical properties from the multi-driver approach previously modelled, and is now employed in the majority of FPGAs sold. Second, the new release can now model a heterogeneous selection of hard logic blocks, which could include the hard memory and multipliers that are now ubiquitous in FPGAs. Third, we provide optimized electrical models of a wide range of architectures in different process technologies, including a range of area-delay tradeoffs for each single architecture. Prior releases of VPR did not publish even one architecture file with accurate resistance and capacitance parameters. Finally, to maintain robustness and to support future development the release includes a set of regression tests to check functionality and quality of result of the output of the tools. To illustrate the use of the new features, we present a new look at the FPGA area vs. logic block LUT size question that shows that small LUT sizes, with the use of carefully optimized electrical design and single-driver architectures, have better area (relative to 4-LUTs) than previously thought. Another experiment shows that several of the previous architectural results are invariant in moving from multi-driver to single-driver routing architecture and across a range of process technologies.