PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Multilevel k-way hypergraph partitioning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Optimization by simulated annealing: A preliminary computational study for the TSP
WSC '83 Proceedings of the 15th conference on Winter Simulation - Volume 2
Structured ASIC, evolution or revolution?
Proceedings of the 2004 international symposium on Physical design
Measuring the gap between FPGAs and ASICs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
On a Pin Versus Block Relationship For Partitions of Logic Graphs
IEEE Transactions on Computers
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Application specific FPGA using heterogeneous logic blocks
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
Microprocessors & Microsystems
High performance 3-dimensional heterogeneous tree-based FPGA architectures (HT-FPGA)
Proceedings of the 10th FPGAworld Conference
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An application specific FPGA (ASIF) is an FPGA with reduced flexibility and improved density. A heterogeneous ASIF is reduced from a heterogeneous FPGA for a predefined set of applications. This work presents a new tree-based heterogeneous ASIF and uses two sets of open core benchmarks to explore the effect of lookup table (LUT) and arity size on it. For tree-based ASIF, LUT size is varied from 3 to 7 while arity size is varied from 4 to 8 and 16. Experimental results show that smaller LUTs with higher arity sizes produce good area results. However, smaller LUTs produce worse results in terms of delay. Further experimental results show that for tree-based ASIF, the combination LUT 4 with arity 16 for SET I and LUT 3 with arity 16 for SET II gives best results in terms of area-delay product. Area comparison between mesh and tree-based ASIFs shows that tree-based ASIF gives 11.27% routing area gain for SET I and gives almost same area results for SET II while consuming 70.30% and 69.80% less wires for SET I and SET II benchmarks respectively. Finally the quality analysis shows that tree-based ASIF produces around 18% better results compared to mesh-based ASIF.