Technology and design challenges for low power and high performance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
The role of custom design in ASIC Chips
Proceedings of the 37th Annual Design Automation Conference
Automatic transistor and physical design of FPGA tiles from an architectural specification
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
A hybrid ASIC and FPGA architecture
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Topological Analysis for Leakage Prediction of Digital Circuits
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Design, layout and verification of an FPGA using automated tools
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Closing the power gap between ASIC and custom: an ASIC perspective
Proceedings of the 42nd annual Design Automation Conference
Explaining the gap between ASIC and custom power: a custom perspective
Proceedings of the 42nd annual Design Automation Conference
Automatic Design of Area-Efficient Configurable ASIC Cores
IEEE Transactions on Computers
CMOS VLSI Design: A Circuits and Systems Perspective
CMOS VLSI Design: A Circuits and Systems Perspective
Routability-driven white space allocation for fixed-die standard-cell placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Tartan: evaluating spatial computation for whole program execution
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
A synthesizable datapath-oriented embedded FPGA fabric
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
A versatile, low latency HyperTransport core
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
An FPGA-based Pentium® in a complete desktop system
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Performance and yield enhancement of FPGAs with within-die variation using multiple configurations
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Architectural implications of brick and mortar silicon manufacturing
Proceedings of the 34th annual international symposium on Computer architecture
Speedups in embedded systems with a high-performance coprocessor datapath
ACM Transactions on Design Automation of Electronic Systems (TODAES)
GlitchMap: an FPGA technology mapper for low power considering glitches
Proceedings of the 44th annual Design Automation Conference
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Desktop Computer with a Reconfigurable Pentium®
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special edition on the 15th international symposium on FPGAs
TORCH: a design tool for routing channel segmentation in FPGAs
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
The amorphous FPGA architecture
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
An open-source HyperTransport core
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Modular array structure for non-restoring square root circuit
Journal of Systems Architecture: the EUROMICRO Journal
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
A Novel Local Interconnect Architecture for Variable Grain Logic Cell
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
REDEFINE: Runtime reconfigurable polymorphic ASIC
ACM Transactions on Embedded Computing Systems (TECS)
FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation
Proceedings of the 46th Annual Design Automation Conference
A low-power field-programmable gate array routing fabric
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Evaluating variable-grain logic cells using heterogeneous technology mapping
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Design on operator-based reconfigurable hardware architecture and cell circuit
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
Multi-port abstraction layer for FPGA intensive memory exploitation applications
Journal of Systems Architecture: the EUROMICRO Journal
VoteBox nano: a smaller, stronger FPGA-based voting machine
EVT/WOTE'09 Proceedings of the 2009 conference on Electronic voting technology/workshop on trustworthy elections
Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
From OO to FPGA: fitting round objects into square hardware?
Proceedings of the ACM international conference on Object oriented programming systems languages and applications
A folded pipeline network processor architecture for 100 Gbit/s networks
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Exploring FPGA routing architecture stochastically
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Improving FPGA placement with dynamically adaptive stochastic tunneling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
A hardwired NoC infrastructure for embedded systems on FPGAs
Microprocessors & Microsystems
Enhancing the area efficiency of FPGAs with hard circuits using shadow clusters
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Comparison between heterogeneous mesh-based and tree-based application specific FPGA
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
How soccer players would do stream joins
Proceedings of the 2011 ACM SIGMOD International Conference on Management of data
Exploration of heterogeneous FPGA architectures
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
p-QCA: A Tiled Programmable Fabric Architecture Using Molecular Quantum-Dot Cellular Automata
ACM Journal on Emerging Technologies in Computing Systems (JETC)
The accelerator store: A shared memory framework for accelerator-based systems
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
Achieving middleware execution efficiency: hardware-assisted garbage collection operations
The Journal of Supercomputing
Application specific FPGA using heterogeneous logic blocks
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
On the asymptotic costs of multiplexer-based reconfigurability
Proceedings of the 49th Annual Design Automation Conference
FPGA based efficient on-chip memory for image processing algorithms
Microelectronics Journal
Implementation of FFT on General-Purpose Architectures for FPGA
International Journal of Embedded and Real-Time Communication Systems
Iterative routing algorithm of Inter-FPGA signals for Multi-FPGA prototyping platform
ARC'13 Proceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications
Continuous real-world inputs can open up alternative accelerator designs
Proceedings of the 40th Annual International Symposium on Computer Architecture
LINQits: big data on little clients
Proceedings of the 40th Annual International Symposium on Computer Architecture
Reconfigurable pipelined coprocessor for multi-mode communication transmission
Proceedings of the 50th Annual Design Automation Conference
Selective flexibility: breaking the rigidity of datapath merging
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
SEC'13 Proceedings of the 22nd USENIX conference on Security
Practical models for energy-efficient prefetching in mobile embedded systems
Microprocessors & Microsystems
Frequency optimization objective during system prototyping on multi-FPGA platform
International Journal of Reconfigurable Computing
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This paper presents experimental measurements of the differences between a 90nm CMOS FPGA and 90nm CMOS Standard Cell ASICs in terms of logic density, circuit speed and power consumption. We are motivated to make these measurements to enable system designers to make better informed hoices between these two media and to give insight to FPGA makers on the deficiencies to attack and thereby improve FPGAs. In the paper, we describe the methodology by which the measurements were obtained and we show that, for circuits containing only combinational logic and flip-flops, the ratio of silicon area required to implement them in FPGAs and ASICs is on average 40. Modern FPGAs also contain "hard" blocks such as multiplier/accumulators and block memories and we find that these blocks reduce this average area gap significantly to as little as 21. The ratio of critical path delay, from FPGA to ASIC, is roughly 3 to 4, with less influence from block memory and hard multipliers. The dynamic power onsumption ratio is approximately 12 times and, with hard blocks, this gap generally becomes smaller.