Delay-oriented technology mapping for heterogeneous FPGAs with bounded resources
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Low-energy FPGAs: architecture and design
Low-energy FPGAs: architecture and design
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Design of Interconnection Networks for Programmable Logic
Design of Interconnection Networks for Programmable Logic
Measuring the gap between FPGAs and ASICs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Depending on the granularity of the basic logic cell, reconfigurable devices are classified into two types; fine-grain and coarse-grain devices. In general, each type has its own advantages; therefore, it is difficult to achieve high implementation efficiency in any applications. In this study, we propose a variable grain logic cell (VGLC) architecture. Its key feature is variable granularity which helps create a balance between these two types of device. In this paper, we propose a local interconnect structure, which is a crossbar switch circuit, for the VGLC. In order to discuss the trade-off between the number of circuit resources and flexibility, we proposed different structures and evaluated them. The results showed that a less flexible structure has almost the same effects as a more flexible structure.