Simultaneous buffer and wire sizing for performance and power optimization
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Gate-level synthesis for low-power using new transformations
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor
Digital Technical Journal
Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A minimum total power methodology for projecting limits on CMOS GSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Low-power design methodology and applications utilizing dual supply voltages
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Microprocessor, 1996: A Study of the MPU, Mcu and DSP Markets
Microprocessor, 1996: A Study of the MPU, Mcu and DSP Markets
ARM System-on-Chip Architecture
ARM System-on-Chip Architecture
Pushing ASIC performance in a power envelope
Proceedings of the 40th annual Design Automation Conference
Optimum Power/Performance Pipeline Depth
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Measuring the gap between FPGAs and ASICs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
An architecture for energy efficient sphere decoding
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
Misleading energy and performance claims in sub/near threshold digital systems
Proceedings of the International Conference on Computer-Aided Design
Semi custom design: a case study on SIMD shufflers
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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We investigate differences in power between application-specific integrated circuits (ASICs) and custom integrated circuits, with examples from 0.6um to 0.13um CMOS. A variety of factors cause synthesizable designs to consume '3 to '7 more power. We discuss the shortcomings of typical synthesis flows, and changes to tools and standard cell libraries needed to reduce power. Using these methods, we believe that the power gap between ASICs and custom circuits can be closed to within 2'.