Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing

Future performance challenges in nanometer design

Proceedings of the 38th annual Design Automation Conference

Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique

Proceedings of the 39th annual Design Automation Conference

Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors

Proceedings of the 39th annual Design Automation Conference

Logic synthesis for low power

Logic Synthesis and Verification

Robust SAT-Based Search Algorithm for Leakage Power Reduction

PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation

Subthreshold leakage modeling and reduction techniques

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Standby power optimization via transistor sizing and dual threshold voltage assignment

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Pushing ASIC performance in a power envelope

Proceedings of the 40th annual Design Automation Conference

High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors

Statistical estimation of leakage current considering inter- and intra-die process variation

Proceedings of the 2003 international symposium on Low power electronics and design

Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization

Proceedings of the 2003 international symposium on Low power electronics and design

Coupling delay optimization by temporal decorrelation using dual threshold voltage technique

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power

Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design

Proceedings of the conference on Design, automation and test in Europe - Volume 1

Statistical analysis of subthreshold leakage current for VLSI circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Gate oxide leakage current analysis and reduction for VLSI circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Statistical optimization of leakage power considering process variations using dual-Vth and sizing

Proceedings of the 41st annual Design Automation Conference

Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment

Proceedings of the 41st annual Design Automation Conference

Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation

Proceedings of the 2004 international symposium on Low power electronics and design

Total power optimization through simultaneously multiple-vDD multiple-vTH assignment and device sizing with stack forcing

Proceedings of the 2004 international symposium on Low power electronics and design

A leakage-energy-reduction technique for highly-associative caches in embedded systems

MEDEA '03 Proceedings of the 2003 workshop on MEmory performance: DEaling with Applications , systems and architecture

High performance level conversion for dual VDD design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design

Characterization and modeling of run-time techniques for leakage power reduction

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems

Closing the power gap between ASIC and custom: an ASIC perspective

Proceedings of the 42nd annual Design Automation Conference

An efficient algorithm for statistical minimization of total power under timing yield constraints

Proceedings of the 42nd annual Design Automation Conference

Self-Compensating Design for Focus Variation

Proceedings of the 42nd annual Design Automation Conference

Full-chip analysis of leakage power under process variations, including spatial correlations

Proceedings of the 42nd annual Design Automation Conference

Leakage minimization of nano-scale circuits in the presence of systematic and random variations

Proceedings of the 42nd annual Design Automation Conference

Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Technology mapping for low leakage power and high speed with hot-carrier effect consideration

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization

Proceedings of the 2006 international symposium on Physical design

LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design

General transistor-level methodology on VLSI low-power design

GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI

Statistical technology mapping for parametric yield

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

Reducing dynamic and leakage energy in VLIW architectures

ACM Transactions on Embedded Computing Systems (TECS)

Timing driven power gating

Proceedings of the 43rd annual Design Automation Conference

Prediction of leakage power under process uncertainties

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors

Proceedings of the 2007 international symposium on Physical design

A high-level clustering algorithm targeting dual Vdd FPGAs

ACM Transactions on Design Automation of Electronic Systems (TODAES)

A new algorithm for simultaneous gate sizing and threshold voltage assignment

Proceedings of the 2009 international symposium on Physical design

GPU-based parallelization for fast circuit optimization

Proceedings of the 46th Annual Design Automation Conference

Minimizing leakage power of sequential circuits through mixed-Vt flip-flops and multi-Vt combinational gates

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Total Power Optimization for Combinational Logic Using Genetic Algorithms

Journal of Signal Processing Systems

Sleep transistor sizing for leakage power minimization considering charge balancing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A new algorithm for simultaneous gate sizing and threshold voltage assignment

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Full-chip leakage analysis for 65nm CMOS technology and beyond

Integration, the VLSI Journal

Dual-Vt assignment policies in ITD-aware synthesis

Microelectronics Journal

Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical design

Proceedings of the 2010 Asia and South Pacific Design Automation Conference

Lagrangian relaxation for gate implementation selection

Proceedings of the 2011 international symposium on Physical design

GPU-Based Parallelization for Fast Circuit Optimization

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Exploiting dynamic micro-architecture usage in gate sizing

Microprocessors & Microsystems

Post sign-off leakage power optimization

Proceedings of the 48th Design Automation Conference

Improving dual Vt technology by simultaneous gate sizing and mechanical stress optimization

Proceedings of the International Conference on Computer-Aided Design

Parametric yield-driven resource binding in high-level synthesis with multi-Vth/Vdd library and device sizing

Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology

Discrete sizing for leakage power optimization in physical design: A comparative study

ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems