Full-chip leakage analysis for 65nm CMOS technology and beyond

Authors:
Jiying Xue;Tao Li;Yangdong Deng;Zhiping Yu
Affiliations:
Institute of Microelectronics, Tsinghua University, Beijing 100084, China;Institute of Microelectronics, Tsinghua University, Beijing 100084, China;Institute of Microelectronics, Tsinghua University, Beijing 100084, China;Institute of Microelectronics, Tsinghua University, Beijing 100084, China
Venue:
Integration, the VLSI Journal
Year:
2010

Citing 24
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Abstract

This work proposes a full-chip leakage analysis framework for 65nm technology and beyond. Analytical models are first constructed to capture the impact of process parameters on leakage current. Then a methodology is introduced to characterize leakage-related process variations in a systematic manner. On such a basis, an efficient procedure is developed to analyze the state-dependent power dissipation due to leakage of a large circuit block by taking into account different leakage mechanisms. Unlike many traditional approaches that rely on log-normal approximations, the proposed algorithm applies a quadratic model of the logarithm for the full-chip leakage current. It is able to handle both Gaussian and non-Gaussian parameter distributions. The model is validated with test chips manufactured with a commercial 65nm CMOS process. Validation results prove that the proposed modeling methodology could achieve a higher accuracy than that from existing methods. Moreover, a full-chip leakage analysis using the developed model can be orders of magnitude faster than a Monte Carlo based approach.