ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
RADAR: RET-aware detailed routing using fast lithography simulations
Proceedings of the 42nd annual Design Automation Conference
Standard cell characterization considering lithography induced variations
Proceedings of the 43rd annual Design Automation Conference
A unified non-rectangular device and circuit simulation model for timing and power
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Design rule optimization of regular layout for leakage reduction in nanoscale design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Investigation of diffusion rounding for post-lithography analysis
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 45th annual Design Automation Conference
Proceedings of the 45th annual Design Automation Conference
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Electrically driven optical proximity correction based on linear programming
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A framework for early and systematic evaluation of design rules
Proceedings of the 2009 International Conference on Computer-Aided Design
Total sensitivity based dfm optimization of standard library cells
Proceedings of the 19th international symposium on Physical design
Performance-based optical proximity correction methodology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling and analysis of the nonrectangular gate effect for postlithography circuit simulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Full-chip leakage analysis for 65nm CMOS technology and beyond
Integration, the VLSI Journal
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Leakage reduction through optimization of regular layout parameters
Microelectronics Journal
PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method
Proceedings of the 49th Annual Design Automation Conference
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In the nano regime it has become increasingly important to consider the impact of non-rectangular gate (NRG) shape caused due to sub-wavelength lithography. NRG dramatically increases the leakage current and requires geometry dependent transistor models for post-litho circuit simulation. In this paper, we propose a coherent modeling approach for non-rectangular gates based on equivalent gate length (Le). A gate-voltage dependent model of Le is developed which is scalable with design conditions, continuous across weak and strong inversion regions, accurate for both leakage and saturation current, and compatible with standard circuit analysis tools. We systematically verify this approach with 65nm TCAD simulations. A generic CAD algorithm is further proposed to predict the value of Le under various non-rectangular geometries. The interaction with the narrow-width effect is efficiently convolved in this method. Depending on the gate geometry, the leakage current can vary more than 15X at 65nm technology node. Our analytical method well captures this effect. Finally, we extrapolate the impact of NRG effect on future technology generations. The proposed model can be easily extracted from TCAD tools or direct silicon data. It bridges the gap between lithography, simulation, and circuit analysis for measuring transistor performance under increasingly severe NRG effect.