A new method to improve accuracy of parasitics extraction considering sub-wavelength lithography effects

Authors:
Kuen-Yu Tsai;Wei-Jhih Hsieh;Yuan-Ching Lu;Bo-Sen Chang;Sheng-Wei Chien;Yi-Chang Lu
Affiliations:
National Taiwan University, Taipei, Taiwan;National Taiwan University, Taipei, Taiwan;National Taiwan University, Taipei, Taiwan;National Taiwan University, Taipei, Taiwan;National Taiwan University, Taipei, Taiwan;National Taiwan University, Taipei, Taiwan
Venue:
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Year:
2010

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Abstract

Modern nanometer integrated circuits are patterned by sub-wavelength lithography with significant shape deviation from drawn layouts. Full-chip parasitics extraction faces new challenges since shape distortions such as line end rounding and corner rounding cannot be accurately characterized by existing layout parameter extraction (LPE) techniques which assume perfect polygons. A new LPE method and efficient shape approximation algorithms are proposed to account for the shape distortions. Preliminary results verified by field solver simulations indicate that accuracy of parasitics extraction can be significantly improved.