DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Efficient thee-dimensional extraction based on static and full-wave layered Green's functions
DAC '98 Proceedings of the 35th annual Design Automation Conference
A multiscale method for fast capacitance extraction
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Electromagnetic parasitic extraction via a multipole method with hierarchical refinement
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 41st annual Design Automation Conference
A precorrected-FFT method for electrostatic analysis of complicated 3-D structures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fast hierarchical algorithm for three-dimensional capacitance extraction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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In modern VLSI circuits, metal conductors are separated by multiple planar, conformal or embedded dielectric media. Previous algorithms based on Boundary Element Method (BEM) are inefficient to extract interconnect capacitance due to the complex dielectric structures. In this paper, we present a new algorithm that combines multilayer Green's function with the equivalent charge method to efficiently deal with the complex dielectrics. The multilayer Green's function is efficient to model layered dielectric media, while the equivalent charge method is powerful to model non-planar complex dielectric. Our method can also model ground plane and reflective boundary wall. From experimental results, the new method is significantly faster than previous methods in realistic conditions, i.e., 70X speedup and 99% memory saving compared with FastCap and 2X speedup and 80% memory saving compared with PHiCap for complex dielectric structure with similar accuracy.