SubCALM: A Program for Hierarchical Substrate Coupling Simulation on Floorplan Level
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Proceedings of the 41st annual Design Automation Conference
New multipole method for 3-D capacitance extraction
Journal of Computer Science and Technology
Proceedings of the 42nd annual Design Automation Conference
Parasitics extraction involving 3-D conductors based on multi-layered Green's function
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Improving boundary element methods for parasitic extraction
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Efficient statistical capacitance variability modeling with orthogonal principle factor analysis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 46th Annual Design Automation Conference
Variational capacitance extraction and modeling based on orthogonal polynomial method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The authors present a new algorithm for computing the capacitance of three-dimensional electrical conductors of complex structures. The new algorithm is significantly faster and uses much less memory than previous best algorithms and is kernel independent. The new algorithm is based on a hierarchical algorithm for the n-body problem and is an acceleration of the boundary element method (BEM) for solving the integral equation associated with the capacitance extraction problem. The algorithm first adaptively subdivides the conductor surfaces into panels according to an estimation of the potential coefficients and a user-supplied error bound. The algorithm stores the potential coefficient matrix in a hierarchical data structure of size O(n), although the matrix is size n2 if expanded explicitly, where n is the number of panels. The hierarchical data structure allows the multiplication of the coefficient matrix with any vector in O (n) time. Finally, a generalized minimal residual algorithm is used to solve m linear systems each of size n × n in O(mn) time, where m is the number of conductors. The new algorithm is implemented and the performance is compared with previous best algorithms for the k × k bus example. The new algorithm is 60 times faster than FastCap and uses 1/80 of the memory used by FastCap. The results computed by the new algorithm are within 2.5% from that computed by FastCap. The new algorithm is 5 to 150 times faster than the commercial software QuickCap with the same accuracy