Design and verification of high-speed VLSI physical design

Authors:
Dian Zhou;Rui-Ming Li
Affiliations:
Department of Electrical Engineering, The University of Texas at Dallas, Richardson, TX and School of Microelectronics, Fudan University, Shanghai, P.R. China;Department of Electrical Engineering, The University of Texas at Dallas, Richardson, TX
Venue:
Journal of Computer Science and Technology
Year:
2005

Citing 118
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Abstract

With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provide readers with some recent progress of the VLSI physical designs. The recent developments of floorplanning and placement, interconnect effects, modeling and delay, buffer insertion and wire sizing, circuit order reduction, power grid analysis, parasitic extraction, and clock signal distribution are briefly reviewed.