Interconnect design for deep submicron ICs

Authors:
Jason Cong;Zhigang Pan;Lei He;Cheng-Kok Koh;Kei-Yong Khoo
Affiliations:
Computer Science Department, University of California, Los Angeles, CA;Computer Science Department, University of California, Los Angeles, CA;Computer Science Department, University of California, Los Angeles, CA;Computer Science Department, University of California, Los Angeles, CA;Computer Science Department, University of California, Los Angeles, CA
Venue:
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Year:
1997

Citing 24
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Principles of CMOS VLSI design: a systems perspective

Principles of CMOS VLSI design: a systems perspective
High-performance routing trees with identified critical sinks

DAC '93 Proceedings of the 30th international Design Automation Conference
Performance-driven interconnect design based on distributed RC delay model

DAC '93 Proceedings of the 30th international Design Automation Conference
RC interconnect synthesis—a moment fitting approach

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Simultaneous driver and wire sizing for performance and power optimization

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Efficient linear circuit analysis by Pade´ approximation via the Lanczos process

EURO-DAC '94 Proceedings of the conference on European design automation
Timing driven placement for large standard cell circuits

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
The Elmore delay as bound for RC trees with generalized input signals

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Reduced-order modeling of large linear subcircuits via a block Lanczos algorithm

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Simultaneous gate and interconnect sizing for circuit-level delay optimization

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Optimal wire sizing and buffer insertion for low power and a generalized delay model

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Stable and efficient reduction of substrate model networks using congruence transforms

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Optimal wiresizing for interconnects with multiple sources

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Optimal non-uniform wire-sizing under the Elmore delay model

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Buffered Steiner tree construction with wire sizing for interconnect layout optimization

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
An efficient approach to simultaneous transistor and interconnect sizing

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Performance optimization of VLSI interconnect layout

Integration, the VLSI Journal
Simultaneous buffer and wire sizing for performance and power optimization

ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Optimal wiresizing under the distributed Elmore delay model

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Global interconnect sizing and spacing with consideration of coupling capacitance

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Interconnect layout optimization under higher-order RLC model

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Switch-level delay models for digital MOS VLSI

DAC '84 Proceedings of the 21st Design Automation Conference
A Sensitivity-Based Wiresizing Approach to Interconnect Optimization of Lossy Transmission Line Topologies

MCMC '96 Proceedings of the 1996 IEEE Multi-Chip Module Conference (MCMC '96)

Calculation of ramp response of lossy transmission lines using two-port network functions

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Shaping a VLSI wire to minimize delay using transmission line model

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MOCSYN: multiobjective core-based single-chip system synthesis

DATE '99 Proceedings of the conference on Design, automation and test in Europe
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Measuring routing congestion for multi-layer global routing

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A hybrid dynamic/quadratic programming algorithm for interconnect tree optimization

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Planning buffer locations by network flows

ISPD '00 Proceedings of the 2000 international symposium on Physical design
Routability-driven repeater block planning for interconnect-centric floorplanning

ISPD '00 Proceedings of the 2000 international symposium on Physical design
Performance analysis and optimization of latency insensitive systems

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TICER: realizable reduction of extracted RC circuits

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Integrated floorplanning and interconnect planning

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Buffer block planning for interconnect-driven floorplanning

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Explicit formulas and efficient algorithm for moment computation of coupled RC trees with lumped and distributed elements

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Layout aware retiming

GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
An interconnect topology optimization by a tree transformation

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Faster and more accurate wiring evaluation in interconnect-centric floorplanning

GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
An efficient analytical model of coupled on-chip RLC interconnects

Proceedings of the 2001 Asia and South Pacific Design Automation Conference
An interconnect energy model considering coupling effects

Proceedings of the 38th annual Design Automation Conference
Buffer block planning for interconnect planning and prediction

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Parametric timing and power macromodels for high level simulation of low-swing interconnects

Proceedings of the 2002 international symposium on Low power electronics and design
Potential slack: an effective metric of combinational circuit performance

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A new algorithm for routing tree construction with buffer insertion and wire sizing under obstacle constraints

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Formulae and applications of interconnect estimation considering shield insertion and net ordering

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An integrated floorplanning with an efficient buffer planning algorithm

Proceedings of the 2003 international symposium on Physical design
Routing methodology for minimizing 1nterconnect energy dissipation

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Repeater and current-sensing hybrid circuits for on-chip interconnects

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Reduction of coupling effects by optimizing the 3-D configuration of the routing grid

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Net Clustering Based Constructive and Iterative Improvement Approaches for Macro-Cell Placement

Journal of VLSI Signal Processing Systems
CNB: a critical-network-based timing optimization method for standard cell global routing

Journal of Computer Science and Technology
Delay-related secondary objectives for rectilinear Steiner minimum trees

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Performance-driven register insertion in placement

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Abstract

In this paper, we study the interconnect layout optimization problem under a higher-order RLC model to optimize not just delay, but also waveform for RLC circuits with non-monotone signal response. We propose a unified approach that considers topology optimization, wiresizing optimization, and waveform optimization simultaneously. Our algorithm considers a large class of routing topologies, ranging from shortest-path Steiner trees to bounded-radius Steiner trees and Steiner routings. We construct a set of required-arrival-time Steiner trees or RATS-trees, providing a smooth trade-off among signal delay, waveform, and routing area. Using a new incremental moment computation algorithm, we interleave topology construction with moment computation to facilitate accurate delay calculation and evaluation of waveform quality. Experimental results show that our algorithm is able to construct a set of topologies providing a smooth trade-off among signal delay, signal settling time, voltage overshoot, and routing cost.