Optimization of power dissipation and skew sensitivity in clock buffer synthesis
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Bounded-skew clock and Steiner routing under Elmore delay
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Optimal wire sizing and buffer insertion for low power and a generalized delay model
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Optimal wiresizing for interconnects with multiple sources
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimal wiresizing for interconnects with multiple sources
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Buffered Steiner tree construction with wire sizing for interconnect layout optimization
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Optimization of custom MOS circuits by transistor sizing
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
An efficient approach to simultaneous transistor and interconnect sizing
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Simultaneous buffer and wire sizing for performance and power optimization
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Power Optimization in VLSI Layout: A Survey
Journal of VLSI Signal Processing Systems
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Delay and Power Expressions for a CMOS Inverter Drivinga Resistive-Capacitive Load
Analog Integrated Circuits and Signal Processing - Special issue: analog design issues in digital VSLI circuits and systems
Optimization techniques for high-performance digital circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Interconnect design for deep submicron ICs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Performance driven global routing for standard cell design
Proceedings of the 1997 international symposium on Physical design
Minimization of chip size and power consumption of high-speed VLSI buffers
Proceedings of the 1997 international symposium on Physical design
Migration: a new technique to improve synthesized designs through incremental customization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Bounded-skew clock and Steiner routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-Power Design for Real-Time Systems
Real-Time Systems
Low-power design methodology and applications utilizing dual supply voltages
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique
Proceedings of the 2002 international symposium on Physical design
Transistor sizing of energy-delay--efficient circuits
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT
Journal of VLSI Signal Processing Systems
Geometric programming for circuit optimization
Proceedings of the 2005 international symposium on Physical design
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Digital Circuit Optimization via Geometric Programming
Operations Research
Proceedings of the 2009 international symposium on Physical design
Power characteristics of inductive interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we study the simultaneous driver and wire sizing (SDWS) problem under two objective functions: i) delay minimization only, or ii) combined delay and power dissipation minimization. We present general formulations of the SDWS problem under these two objectives based on the distributed Elmore delay model with consideration of both capacitive power dissipation and short-circuit power dissipation. We show several interesting properties of the optimal SDWS solutions under the two objectives, including an important result which reveals the relationship between driver sizing and optimal wire sizing. These results lead to polynomial time algorithms for computing the lower and upper bounds of optimal SDWS solutions under the two objectives, and efficient algorithms for computing optimal SDWS solutions under the two objectives. We have implemented these algorithms and compared them with existing design methods for driver sizing only or independent driver and wire sizing. Accurate SPICE simulation shows that our methods reduce the delay by up to 12%-49% and power dissipation by 26%-63% compared with existing design methods.