IEEE Transactions on Computers
Analysis and design of latch-controlled synchronous digital circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Computing optimal clock schedules
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Process-variation-tolerant clock skew minimization
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Simultaneous driver and wire sizing for performance and power optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal clock skew scheduling tolerant to process variations
DAC '96 Proceedings of the 33rd annual Design Automation Conference
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Optimal wiresizing under the distributed Elmore delay model
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Reduced Delay Uncertainty in High Performance Clock Distribution Networks
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Clock Skew Scheduling Under Process Variations
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Proceedings of the 46th Annual Design Automation Conference
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An integrated top-down design system is presented in this paper forsynthesizing clock distribution networks for application tosynchronous digital systems. The timing behavior of a synchronousdigital circuit is obtained from the register transfer leveldescription of the circuit, and used to determine a non-zero clockskew schedule which reduces the clock period as compared to zeroskew-based approaches. Concurrently, the permissible range ofclock skew for each local data path is calculated to determine themaximum allowed variation of the scheduled clock skew such that nosynchronization failures occur. The choice of clock skew valuesconsiders several design objectives, such as minimizing the effectsof process parameter variations, imposing a zero clock skewconstraint among the input and output registers, and constraining thepermissible range of each local data path to a minimum value.The clock skew schedule and the worst case variation of the primary processparameters are used to determine the hierarchical topology of the clockdistribution network, defining the number of levels and branches of theclock tree and the delay associated with each branch. The delay of eachbranch of the clock tree is physically implemented with distributed bufferstargeted in CMOS technology using a circuit model that integratesshort-channel devices with the signal waveform shape and the characteristicsof the clock tree interconnect. A bottom-up approach for calculating theworst case variation of the clock skew due to process parameter variations isintegrated with the top-down synthesis system. Thus, the local clock skewsand a clock distribution network are obtained which are more tolerant toprocess parameter variations.This methodology and related algorithms have been demonstrated on severalMCNC/ISCAS-89 benchmark circuits. Increases in system-wide clock frequencyof up to 43% as compared with zero clock skew implementationsare shown. Furthermore, examples of clock distribution networks that exploitintentional localized clock skew are presented which are tolerant to processparameter variations with worst case clock skew variations of up to 30%.