Timing driven placement using complete path delays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
An adaptive timing-driven layout for high speed VLSI
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-performance routing trees with identified critical sinks
DAC '93 Proceedings of the 30th international Design Automation Conference
Performance-driven interconnect design based on distributed RC delay model
DAC '93 Proceedings of the 30th international Design Automation Conference
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Signal Delay in RC Tree Networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simultaneous driver and wire sizing for performance and power optimization
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
RC interconnect synthesis—a moment fitting approach
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
RC interconnect optimization under the Elmore delay model
DAC '94 Proceedings of the 31st annual Design Automation Conference
Simultaneous gate and interconnect sizing for circuit-level delay optimization
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Post routing performance optimization via tapered link insertion and wiresizing
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
A sequential quadratic programming approach to concurrent gate and wire sizing
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Post routing performance optimization via multi-link insertion and non-uniform wiresizing
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Optimal wiresizing for interconnects with multiple sources
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Sizing of clock distribution networks for high performance CPU chips
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Interconnect design for deep submicron ICs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
EWA: exact wiring-sizing algorithm
Proceedings of the 1997 international symposium on Physical design
Greedy wire-sizing is linear time
ISPD '98 Proceedings of the 1998 international symposium on Physical design
A parallel algorithm for zero skew clock tree routing
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Interconnect estimation and planning for deep submicron designs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Equivalent Elmore delay for RLC trees
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Mixing buffers and pass transistors in FPGA routing architectures
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
RC(L) interconnect sizing with second order considerations via posynomial programming
Proceedings of the 2001 international symposium on Physical design
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Shaping a VLSI Wire to Minimize Elmore Delay
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Clock network sizing via sequential linear programming with time-domain analysis
Proceedings of the 2004 international symposium on Physical design
Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
Self-heating-aware optimal wire sizing under Elmore delay model
Proceedings of the conference on Design, automation and test in Europe
The coming of age of physical synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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