Long path enumeration algorithms for timing verification on large digital systems
Graph theory with applications to algorithms and computer science
Algorithms for physical design of `sea-of-gates' chips
Computer-Aided Design
ORCA a sea-of-gates place and route system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Performance-driven placement of cell based IC's
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Timing influenced layout design
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Adaptive Control Systems: Techniques and Applications
Adaptive Control Systems: Techniques and Applications
Chip layout optimization using critical path weighting
DAC '84 Proceedings of the 21st Design Automation Conference
Fuzzy logic approach to placement problem
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
The role of timing verification in layout synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Dynamic prediction of critical paths and nets for constructive timing-driven placement
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Performance oriented rectilinear Steiner trees
DAC '93 Proceedings of the 30th international Design Automation Conference
Prime: a timing-driven placement tool using a piecewise linear resistive network approach
DAC '93 Proceedings of the 30th international Design Automation Conference
An efficient timing-driven global routing algorithm
DAC '93 Proceedings of the 30th international Design Automation Conference
Rectilinear Steiner trees with minimum Elmore delay
DAC '94 Proceedings of the 31st annual Design Automation Conference
Optimal wiresizing under the distributed Elmore delay model
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
| Hi-index | 0.00 |
An adaptive timing-driven layout system, called JUNE, has been developed. The constructive algorithm, which combines placement with the global routing, constructs a placement satisfying timing and routability constraints. The placement problem for each macro is solved hierarchically as a sequence of two optimization problems followed by an adaptive correction procedure. Experimental results for industrial sea-of-gates chips confirmed effectiveness of this approach.