ORCA a sea-of-gates place and route system

Authors:
M. Igusa;M. Beardslee;A. Sangiovanni-Vicentelli
Affiliations:
Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California;Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California;Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California
Venue:
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Year:
1989

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Abstract

Sea-of-gates is becoming an important design style for Application Specific Integrated Circuits (ASICs). The sea-of-gates technology offers more flexible placement and routing options not available in gate arrays. Very few systems are available today that can automatically layout sea-of-gates and none of these systems effectively use the features available in sea-of-gates architecture. ORCA is a place and route system for sea-of-gates, whose objective is to produce the highest density layout by fully exploiting the inherent features of this new design style. The ORCA system starts with a module generator which preprocesses memory arrays and other logic with a regular structure to form high density macros. The remaining logic is clustered together to form flexible macros, which we call porous. The porous macro-cells allow global routing to pass through the macro instead of detouring around its perimeter. The porous macros are dynamically shaped and resized by interaction with global wiring analysis. Finally, a general channelless area router has been developed to address the multiple layers of interconnect and routing areas which will be dominantly over-the-cell. Due to the large size of the problem (e.g. 100,000 gates), the placement and routing algorithms are hierarchical.