The chip layout problem: An automatic wiring procedure

  • Authors:
  • K. A. Chen;M. Feuer;K. H. Khokhani;N. Nan;S. Schmidt

  • Affiliations:
  • -;-;-;-;-

  • Venue:
  • DAC '77 Proceedings of the 14th Design Automation Conference
  • Year:
  • 1977

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Abstract

This paper describes an automatic system for routing the metal connections on integrated circuit chips. The system contains three major sections: global wiring, vertical channel assignment, and horizontal bilateral channel allocation. Since its initial development in 1972, this system has been used successfully at IBM in the physical design of bipolar logic chips.