IBM FSD VLSI chip design methodology
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '76 Proceedings of the 13th Design Automation Conference
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
Prediction of wiring space requirements for LSI
DAC '77 Proceedings of the 14th Design Automation Conference
The chip layout problem: An automatic wiring procedure
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
A new circuit placement program for FET chips
DAC '79 Proceedings of the 16th Design Automation Conference
A placement capability based on partitioning
DAC '79 Proceedings of the 16th Design Automation Conference
IBM Journal of Research and Development
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The Federal Systems Division has developed a structured design methodology and a companion chip physical design system that has been used to build seven large VLSI chips (ranging in size from 7K to 36K logic primitives). Using the MVISA system, a logic designer has complete control and responsibility for the total chip design. Our experience has been that when this highly interactive software and methodology is used, chip physical design requires less than two weeks. This is a significant savings in design time; but more importantly the designer can allocate more schedule for logic design and simulation. This paper describes how FSD's unique interactive physical design system has improved productivity of VLSI design.